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| CY28800 100-MHz Differential Buffer for PCI Express and SATA Features * CK409 and CK410 companion buffer * Eight differential 0.7V clock output pairs * OE_INV input for inverting OE, PWRDWN, and SRC_STP active levels * Individual OE controls * Low CTC jitter (< 50 ps) * Programmable bandwidth * SRC_STP power management control * SMBus Block/Byte/Word Read and Write support * 3.3V operation * PLL Bypass-configurable * Divide by 2 programmable * 48-pin SSOP package Functional Description The CY28800 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. Block Diagram SRC_DIV2# VDD VSS SRCT_IN SRCC_IN OE_0 OE_3 DIFT0 DIFCO VSS VDD DIFT1 DIFC1 OE_1 OE_2 DIFT2 DIFC2 VSS VDD DIFT3 DIFC3 PLL/BYPASS# SCLK SDATA Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_A VSS_A IREF LOCK OE_7 OE_4 DIFT7 DIFC7 OE_INV VDD DIFT6 DIFC6 OE_6 OE_5 DIFT5 DIFC5 VSS VDD DIFT4 DIFC4 HIGH_BW# SRC_STP PWRDWN VSS PWRDWN OE_[7:0] OE_INV SRC_STP SCLK SDATA SMBus Controller Output Control DIFT_0 DIFC_0 DIFT_1 DIFC_1 DIFT_2 DIFC_2 DIFT_3 DIFC_3 PLL/BYPASS# DIV SRCT_IN SRCC_IN DIFT_4 DIFC_4 DIFT_5 DIFC_5 DIFT_6 DIFC_6 DIFT_7 DIFC_7 HIGH_BW# PLL1 CY28800 SRC_DIV2# Output Buffer 48 SSOP Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 15 www.SpectraLinear.com CY28800 Pin Description Pin 4,5 Name SRCT_IN, SRCC_IN Type I,DIF 0.7V Differential inputs Description 8,9;12,13;16,17;20,21; 30,29; DIF[T/C][7:0] 34,33;38,37;42,41 6,7,14,15,35,36,43,44 OE_[7:0] O,DIF 0.7V Differential Clock Outputs I,SE 3.3V LVTTL input for enabling differential outputs Active High if OE_INV = 0 Active Low if OE_INV = 1 3.3V LVTTL input for selecting PLL bandwidth 0 = High BW, 1 = Low BW 3.3V LVTTL output, transitions high when PL lock is achieved (latched output) 3.3V LVTTL input for Power Down Active Low if OE_INV = 0 Active High if OE_INV = 1 3.3V LVTTL input for selecting input frequency divided by two, active low 3.3V LVTTL input for SRC_STP. Disables stoppable outputs. Active Low if OE_INV = 0 Active High if OE_INV = 1 SMBus Slave Clock Input A precision resistor is attached to this pin to set the differential output current 3.3V LVTTL input for selecting fan-out or PLL operation 3.3V Power Supply for PLL Ground for PLL Ground for outputs 3.3V power supply for outputs Input strap for setting polarity of OE_[7:0], SRC_STP, and PWRDWN 28 45 26 HIGH_BW# LOCK PWRDWN I,SE O,SE I,SE 1 27 SRC_DIV2# SRC_STP I,SE I,SE 23 24 46 22 48 47 3,10,18,25,32 2,11,19,31,39 40 SCLK SDATA IREF PLL/BYPASS# VDD_A VSS_A VSS VDD OE_INV I,SE I I PWR GND GND PWR I, SE I/O,OC Open collector SMBus data Serial Data Interface To enhance the flexibility and function of the clock buffer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11011100 (DCh). Table 1. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Description Rev 1.0, November 21, 2006 Page 2 of 15 CY28800 Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count from master - 8 bits Acknowledge from slave Data byte 0 from master - 8 bits Acknowledge from slave Data byte 1 from master - 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from host Data byte 0 from slave - 8 bits Acknowledge from host Data byte 1 from slave - 8 bits Acknowledge from host Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Acknowledge from host Stop Block Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Rev 1.0, November 21, 2006 Page 3 of 15 CY28800 Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @pup 0 0 0 0 0 1 1 1 Name PWRDWN Drive Mode SRC_STP Drive Mode Reserved Reserved Reserved HIGH_BW# PLL/BYPASS# SRC_DIV2# Description Power Down drive mode 0 = Driven when stopped, 1 = Tri-state SRC Stop drive mode 0 = Driven when stopped, 1 = Tri-state Reserved Reserved Reserved HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth PLL/BYPASS# 0 = Fanout buffer, 1 = PLL mode SRC_DIV2# configures output frequency at half the input frequency 0 = Divided by 2 mode (output = input/2),1 = Normal (output = input) Byte 1: Control Register 1 Bit 7 @pup 1 OE_7 Name DIF[T/C]7 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]6 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]5 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]4 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]3 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]2 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]1 Output Enable 0 = Disabled (Tri-state) 1 = Enabled DIF[T/C]0 Output Enable 0 = Disabled (Tri-state) 1 = Enabled Description 6 1 OE_6 5 1 OE_5 4 1 OE_4 3 1 OE_3 2 1 OE_2 1 1 OE_1 0 1 OE_0 Byte 2: Control Register 2 Bit 7 @pup 0 Name SRC_STP_DIF[T/C]7 Description Allow Control DIF[T/C]7 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]6 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]5 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 6 0 SRC_STP_DIF[T/C]6 5 0 SRC_STP_DIF[T/C]5 Rev 1.0, November 21, 2006 Page 4 of 15 CY28800 Byte 2: Control Register 2 (continued) Bit 4 @pup 0 Name SRC_STP_DIF[T/C]4 Description Allow Control DIF[T/C]4 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]3 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]2 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]1 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]0 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 3 0 SRC_STP_DIF[T/C]3 2 0 SRC_STP_DIF[T/C]2 1 0 SRC_STP_DIF[T/C]1 0 0 SRC_STP_DIF[T/C]0 Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Byte 4: Vendor ID Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Rev 1.0, November 21, 2006 Page 5 of 15 CY28800 OE_INV Clarification The OE_INV pin is an input strap sampled at power-on. The functionality of this input is to set the active level polarities for OE_[7:0], PWRDWN, and SRC_STP input pins. `Active High' indicates the functionality of the input is asserted when the input voltage level at the pin is high and deasserted when the voltage level at the input is low. `Active Low' indicates that the functionality of the input is asserted when the voltage level at the input is low and deasserted when the voltage level at the input pin is high. See VIH and VIL in the DC Electrical Specifications for input voltage high and low ranges. OE_INV 0 1 PWRDWN Active Low Active High SRC Active Low Active High OE_[7:0] Active High Active Low glitches, frequency shifting or amplitude abnormalities among others. OE_INV 0 0 1 1 PWRDWN 0 1 0 1 Mode Power Down Normal Normal Power Down PWRDWN Assertion When the power down pin is sampled as being asserted by two consecutive rising edges of DIFC, all DIFT outputs will be held high or Tri-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC high to low transition. When the SMBus PWRDWN Drive Mode bit is programmed to `0', all clock outputs will be held with the DIFT pin driven high at 2 x Iref and DIFC tri-stated. However, if the control register PWRDWN Drive Mode bit is programmed to `1', then both DIFT and the DIFC are Tri-stated. PWRDWN Clarification The PWRDWN pin is an asynchronous input used to shut off all clocks cleanly and instruct the device to evoke power savings mode. It may be active high or active low depending on the strapped value of the OE_INV input. The PWRDWN pin should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN is an asynchronous input for powering up the system. When the PWRDWN pin is asserted, all clocks will be held high or tri-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and meet all AC and DC parameters. This means no PWRDWN DIFT DIFC PWRDWN Deassertion The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable clocks are output from the buffer chip (PLL locked). IF the control register PWRDWN Drive Mode bit is programmed to `1', all differential outputs must be driven high in less than 300 s of the power down pin deassertion to a voltage greater than 200 mV. Figure 1. PWRDWN Assertion Diagram, OE_INV = 0 PWRDWN DIFT DIFC Figure 2. PWRDWN Assertion Diagram, OE_INV = 1 Tstable <1 ms PWRDWN DIFT DIFC Tdrive_Pwrdwn# <300 s, >200 mV Figure 3. PWRDWN Deassertion Diagram, OE_INV = 0 Rev 1.0, November 21, 2006 Page 6 of 15 CY28800 Tstable <1 ms PWRDWN DIFT DIFC Tdrive_Pwrdwn# <300 s, >200 mV Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1 Table 4. Buffer Power-up State Machine State 0 1 2[5] 3[2, 3, 4] 3.3V Buffer power off After 3.3V supply is detected to rise above 1.8V-2.0V, the buffer enters state 1 and initiates a 0.2-ms-0.3-ms delay Buffer waits for PWRDWN deassertion (and a valid clock on the SRC_IN input if in PLL mode) Outputs enabled for normal operation (PLL lock to the SRC_IN input is assured in PLL mode) Description Figure 5. Buffer Power-up State Diagram[1] SRC_STP Clarification The SRC_STP signal is an asynchronous input used for clean stopping and starting the DIFT/C outputs. This input can be Active High or Active Low based on the strapped value of the OE_INV input. The SRC_STP signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) In the case where the output is disabled via OE control, the output will always be tri-stated regardless of the SRC_STP Drive Mode register bit state. Table 5. SRC_STP Functionality[6] OE_INV 0 0 1 1 SRC_STP 1 0 1 0 DIFT Normal Iref * 6 or Float Iref * 6 or Float Normal DIFC Normal Low Low Normal Notes: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. 2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input). 3. LOCK output is a latched signal that is reset with the assertion of PWRDWN or when VDD<1.8V. 4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e., overshoot/undershoot is allowed). 5. In PLL mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled. 6. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state. Rev 1.0, November 21, 2006 Page 7 of 15 CY28800 SRC_STP Assertion The impact of asserting the SRC_STP pin is that all DIF outputs that are set in the control registers to stoppable via assertion of SRC_STP are stopped after their next transition. When the control register SRC_STP three-state bit is programmed to `0', the final state of all stopped DIFT/C signals is DIFT clock = High and DIFC = Low. There will be no change to the output drive current values, DIFT will be driven high with a current value equal 6 x Iref, and DIFC will not be driven. When the control register SRC_STP three-state bit is programmed to `1', the final state of all stopped DIF signals is low, both DIFT clock and DIFC clock outputs will not be driven. SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) SRC_STP Deassertion All differential outputs that were stopped will resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2-6 DIFT/C clock periods (2 clocks are shown) with all DIFT/C outputs resuming simultaneously. If the control register tri-state bit is programmed to `1' (tri-state), then all stopped DIFT outputs will be driven high within 15 ns of SRC_STP deassertion to a voltage greater than 200 mV. 1 ms Figure 6. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 0 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 7. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 0 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 8. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 0 Rev 1.0, November 21, 2006 Page 8 of 15 CY28800 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 9. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 1 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 10. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 1 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 11. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 1 Output Enable Clarification OE functionality allows for enabling and disabling individual outputs. OE_[7:0] are Active High or Active Low inputs depending on the strapped value of the OE_INV input. Disabling the outputs may be implemented in two ways, via writing a `0' to SMBus register bit corresponding to output of interest or by deasserting the OE input pin. In both methods, if SMBus registered bit has been written low or the OE pin is deasserted or both, the output of interest will be tri-stated. (The assertion and deassertion of this signal is absolutely asynchronous.) Table 6. OE Functionality OE_INV 0 0 0 0 1 1 1 1 OE (Pin) 0 0 1 1 0 0 1 1 OE (SMBus Bit) 0 1 0 1 0 1 0 1 DIF[T/C] Tri-State Tri-State Tri-State Enabled Tri-State Enabled Tri-State Tri-State Rev 1.0, November 21, 2006 Page 9 of 15 CY28800 OE Assertion All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2-6 DIF clock periods. In addition, DIFT clocks will be driven high within 15 ns of OE assertion to a voltage greater than 200 mV. function may be implemented in two ways, via writing a `0' to SMBus register bit or by asserting the SRC_DIV2# input pin low. In both methods, if the SMBus register bit has been written low or the SRC_DIV2# pin is low or both, all DIF outputs will configured for divide by 2 operation. SRC_DIV2# Assertion The impact of asserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from normal operation (output frequency equal to input) to half the input frequency within 2-6 DIF clock periods. OE Deassertion The impact of deasserting OE is that each corresponding output will transition from normal operation to tri-state in a glitch-free manner. The maximum latency from the deassertion to tri-stated outputs is between two-six DIF clock periods. SRC_DIV2# Deassertion The impact of deasserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from divide by 2 mode to normal (output frequency is equal to the input frequency) operation within two-six DIF clock periods. LOCK Signal Clarification The LOCK output signal is intended to provide designers a signal indicating that PLL lock has been achieved and valid clock are available. This can be helpful when cascading multiple buffers which each contribute a 1-ms start-up delay in addition to the start-up time of the clock source. Upon receiving a valid clock on the SRC_IN input (PWRDWN deasserted), the buffer will begin ramping the internal PLL until lock is achieved and stable, the clock buffer will assert the LOCK pin high and enable DIF output clocks. In other words, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, all DIF clocks remain disabled. Only after valid input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable are LOCK to be asserted and the DIF outputs enabled. The maximum start-up latency from valid clocks on SRC_IN input to the assertion of LOCK (output clocks are valid) is to be less than 1 ms. Once LOCK has been asserted high, it will remain high (regardless of the actual PLL status) until power is removed or the PWRDWN pin has been asserted. PLL/BYPASS# Clarification The PLL/Bypass# input is used to select between bypass mode (no PLL) and PLL mode. In bypass mode, the input clock is passed directly to the output stage resulting in 50-ps additive jitter (50 ps + input jitter) on DIF outputs. In the case of PLL mode, the input clock is pass through a PLL to reduce high-frequency jitter. The BYPASS# mode may be selected in two ways--via writing a `0' to SMBus register bit or by asserting the PLL/BYPASS# pin low. In both methods, if the SMBus register bit has been written to `0' or PLL/BYPASS# pin is low or both, the device will be configure for BYPASS operation. HIGH_BW# Clarification The HIGH_BW# input is used to set the PLL bandwidth. This mode is intended to minimize PLL peaking when two or more buffers are cascaded by staggering device bandwidths. The PLL high bandwidth mode may be selected in two ways, via writing a `0' to SMBus register bit or by asserting the HIGH_BW# pin is low or both, the device will be configured for high bandwidth operation. SRC_DIV2# Clarification The SRC_DIV2# input is used to configure the DIF output mode to be equal to the SRC_IN input frequency or half the input frequency in a glitch-free manner. The SRC_DIV2# Rev 1.0, November 21, 2006 Page 10 of 15 CY28800 Absolute Maximum Conditions Parameter VDD VDD_A VIN TS TA TJ ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional MIL-STD-883, Method 3015 At 1/8 in. 2000 V-0 1 Condition Min. -0.5 -0.5 -0.5 -65 0 Max. 4.6 4.6 VDD + 0.5 +150 70 150 Unit V V VDC C C C V DC Electrical Specifications Parameter VDD_A, VDD VILI2C VIHI2C VIL VIH VOL VOH IIL IIH CIN COUT LIN IDD3.3V Description 3.3V Operating Voltage Input Low Voltage Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage 3.3V Output Low Voltage 3.3V Output High Voltage Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Dynamic Supply Current At max. load, Full Active Bypass Mode At max. load, Full Active PLL Mode All OE deasserted, Bypass SRC_STP asserted, Outputs Driven, Bypass SRC_STP asserted, Outputs Tri-state, Bypass SRC_STP asserted, Outputs Driven, PLL SRC_STP asserted, Outputs Tri-State, PLL IPD3.3V Power-down Supply Current PWRDWN asserted, Outputs driven PWRDWN asserted, Outputs Tri-stated IOL = 1 mA IOH = -1 mA except internal pull-up resistors, 0 < VIN < VDD except internal pull-down resistors, 0 < VIN < VDD 1.5 -- - - - - - - - - - 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.5 2.0 - 2.4 -5 5 5 6 7 175 200 35 150 2 160 2 65 5 Max. 3.465 1.0 - 0.8 VDD + 0.5 0.4 - Unit V V V V V V V A A pF pF nH mA mA mA mA mA mA mA mA mA AC Electrical Specifications (Measured in High Bandwidth Mode) Parameter SRC_IN at 0.7V TPERIOD T R / TF VIH VIL VOX Average Period DIFT and DIFC Rise and Fall Times Differential Input High Voltage Differential Input Low Voltage Crossing Point Voltage at 0.7V Swing Measured SE 250 Measured at crossing point VOX Measured at crossing point VOX Single ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) 9.9970 9.8720 0.6 150 -150 550 4 10.0533 ns ns V/ns mV mV mV TABSMIN-IN Absolute minimum clock periods Description Condition Min. Max. Unit Rev 1.0, November 21, 2006 Page 11 of 15 CY28800 AC Electrical Specifications (continued)(Measured in High Bandwidth Mode) Parameter VOX VRB TSTABLE VMAX VMIN TDC TRFM DIF at 0.7V FIN FERROR TDC TPERIOD T R / TF TRFM TR/ TF VHIGH VLOW VOX VOX VOVS VUDS VRB TCCJ TSKEW TPD Input Frequency Input/Output Frequency Error DIFT and DIFC Duty Cycle Average Period DIFT and DIFC Rise and Fall Times Rise/Fall Matching Rise and Fall Time Variation Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Vcross Variation over all edges Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Cycle to Cycle Jitter Any DIFT/C to DIFT/C Clock Skew Input to output skew in PLL mode Input to output skew in Non-PLL mode 33 4 9 .9 33 4 9 .9 Description Vcross Variation over all edges Differential Ringback Voltage Time before ringback allowed Absolute maximum input voltage Absolute minimum input voltage DIFT and DIFC Duty Cycle Rise/Fall Matching Measured SE Condition Min. -100 500 Max. 140 100 1.15 Unit mV mV ps V V % % -0.3 Measured at crossing point VOX Determined as a fraction of 2 * (TR - TF)/(TR + TF) Bypass or PLL 1:1 Bypass or PLL 1:1 Measured at crossing point VOX Measured at crossing point VOX at 100 MHz Single ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) Determined as a fraction of 2 * (TR - TF)/(TR + TF) Single ended measurement: VOL = 0.175 to VOH = 0.525V (Real Time) Measured SE Measured SE Measured SE Measured SE Measured SE Measured SE Measured SE PLL Mode Bypass Mode (Jitter is additive) Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX T PCB M e a s u re m e n t P o in t 2 pF 45 - 55 20 90 - 45 9.9970 175 - - 660 -150 250 - - - 0.2 - - - - 2.5 210 0 55 10.0533 700 20 125 850 - 550 140 VHIGH + 0.3 -0.3 N/A 50 50 50 250 4.5 MHz ppm % ns ps % ps mv mv mv mV V V V ps ps ps ps ns D IF T D IF C IR E F 475 T PCB M e a s u re m e n t P o in t 2 pF T r a c e Im p e d a n c e M e a s u r e d D if f e r e n tia lly Figure 12. Differential Clock Termination Rev 1.0, November 21, 2006 Page 12 of 15 CY28800 Switching Waveforms TRise (CLOCK) VOH = 0.525V CL CK OC K# O CL VCROSS VOL = 0.175V TFall (CLOCK) Figure 13. Single-Ended Measurement Points for TRise and TFall V O VS V RB V RB V LO W V UDS Figure 14. Single-ended Measurement Points for VOVS,VUDS and VRB Rev 1.0, November 21, 2006 Page 13 of 15 CY28800 TPERIOD High Duty Cycle % Skew Management Point Low Duty Cycle % 0.000V Figure 15. Differential (Clock-Clock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Rev 1.0, November 21, 2006 Page 14 of 15 CY28800 Ordering Information Ordering Code Lead Free CY28800OXC CY28800OXCT 48-pin SSOP 48-pin SSOP-Tape and Reel Commercial, 0C to 70 C Commercial, 0C to 70 C Package Type Operating Range Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package O48 51 85061 C While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 15 of 15 |
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